M66851FP Ver la hoja de datos (PDF) - MITSUBISHI ELECTRIC

Número de pieza

componentes Descripción

Fabricante

M66851FP

SRAM TYPE FIFO MEMORY

MITSUBISHI ELECTRIC  

MITSUBISHI <DIGITAL ASSP>

M66850J/FP, M66851J/FP

M66852J/FP, M66853J/FP

SRAM TYPE FIFO MEMORY

PIN and SIGNAL DESCRIPTIONS

• VCC

One+5 volt power supply pin.

• GND

One 0 volt ground pin.

• RS : Reset(INPUT)

When RS is set LOW, internal read and write pointers are set to

the first physical location,the output register is initialized to LOW,

FF and PAF are set HIGH, EF and PAE are set LOW.

A reset is required after power-up before a write operation.

• WCLK : Write Clock(INPUT)

Data present on D0-D8 is written into the FIFO on the rising edge

of WCLK when the FIFO is enabled for writing.

• RCLK : Read Clock(INPUT)

Data is read from the FIFO on the rising edge of RCLK when the

FIFO is enabled for reading.

• WEN1 : Write Enable1(INPUT)

If the FIFO is configured to allow loading of the offset registers,

WEN1 is the only the write enable. When WEN1 is LOW, data on

D0-D8 is written to the FIFO on the rising edge of WCLK.

If the FIFO is configured to have two writeenables, data on D0-

D8 is written to the FIFO on the rising edge of WCLK when

WEN1 is LOW and WEN2 is High. But if the FF is LOW, data on

D0-D8 will not be written to the FIFO.

• WEN2/LD : Write Enable2/Load(INPUT)

The function of this signal is defined at reset.

If WEN2/LD is HIGH at reset, this signal functions as a second

write enable(WEN2). If WEN2/LD is LOW at reset, this signal

functions as a control to load and read the offset register.

If the FIFO is configured to have two write enables, data on D0-

D8 is written to the FIFO on the rising edge of WCLK when

WEN1 is LOW and WEN2 is High. But if the FF is LOW, data on

D0-D8 will not be written to the FIFO.

If the FIFO is configured to have programmable flags, it is

possible to write and read from the offset registers. There are

four 9-bit offset registers. Two are used to control the

programmable Almost-Empty Flag and two are used to control the

programmable Almost-Full Flag.

Data on D0-D8 is written to an offset register on the rising edge

of WCLK when WEN1 is LOW and LD is LOW. Data on D0 – D8

is written to the offset registers in the following order :

PAE LSB, PAE MSB, PAF LSB, PAF MSB.

• REN1, REN2 : Read Enable(INPUT)

Data is read from the FIFO and presented Q0-8 on the rising

edge of RCLK, when REN1 and REN2 are LOW and output port

is enabled.

If either Read Enable is HIGH,the output register holds the

previous data.

When the FIFO is empty, the Read Enable signals are ignored.

• OE : Output Enable(INPUT)

When OE is LOW, the output port Q0-8 is enabled for output.

When OE is HIGH, the output port Q0-8 is placed in a high

impedance state.

• D0-8 : Data Input(INPUT)

D0-8 is the 9-bit data input port.

• Q0-8 : Data Output(OUTPUT)

Q0-8 is the 9-bit data Output port.

2

• EF : Empty Flag(OUTPUT)

The Empty flag goes LOW when the read pointer is equal to the

write pointer.

When EF is LOW, the FIFO is empty and further data reads from

the data output are inhibited.

EF is synchronized to the rising edge of RCLK.

• PAE : Programmable Almost-Empty Flag(OUTPUT)

When PAE is LOW, the FIFO is almost empty based on the

offset. The default offset is Empty+7. PAE is synchronized to the

rising edge of RCLK.

• FF : Full Flag(OUTPUT)

When FF is LOW, the FIFO is full and further data writes into the

data input are inhibited.

The Full Flag goes LOW when the FIFO is full of data.

FF is synchronized to the rising edge of WCLK.

• PAF : Programmable Almost-Full Flag(OUTPUT)

When PAF is LOW, the FIFO is almost full based on the offset.

The default offset is Full-7. PAF is synchronized to the rising

edge of WCLK.

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