LSD20463 Ver la hoja de datos (PDF) - Conexant Systems
Número de pieza
componentes Descripción
Fabricante
LSD20463 Datasheet PDF : 68 Pages
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Label
PCICLK
PCIRST#
AD[31:0]
CBE0#
CBE1#
CBE2#
CBE3#
PAR
FRAME#
IRDY#
TRDY#
STOP#
IDSEL
DEVSEL#
REQ#
GNT#
PERR#
SERR#
INTA#
PME#
STSCHG#
SmartHCF Mobile Modem Designer’s Guide
Pin
10
9
15-17, 19-21,
23-24, 28-30,
32-35, 37, 49-
56, 59-62, 64-
67
57
48
38
25
46
39
40
41
43
27
42
13
12
44
45
8
14
14
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I/O Type
Signal Name/Description
PCI BUS INTERFACE
Ip
PCI Bus Clock. The PCICLK (PCI Bus CLK signal) input provides timing for all
(in)
transactions on PCI. Connect to PCI Bus: CLK.
Ip
PCI Bus Reset. Active low input asserted to initialize PCI-specific registers,
(in)
sequencers, and signals to a consistent reset state. Connect to PCI Bus: RST#.
I/Opts
(t/s)
Multiplexed Address and Data. Address and Data are multiplexed on the same PCI
pins. Connect to PCI Bus: AD[31-0].
I/Opts
(t/s)
I/Opts
(t/s)
I/Opsts
(s/t/s)
I/Opsts
(s/t/s)
I/Opsts
(s/t/s)
I/Opsts
(s/t/s)
Ip
(in)
I/Opsts
(s/t/s)
Opts
(t/s)
Ipts
(t/s)
I/Opsts
(s/t/s)
Opod
(o/d)
Opod
(o/d)
Opod
(o/d)
Opod
(o/d)
Bus Command and Bus Enable. Bus Command and Byte Enables are multiplexed
on the same PCI pins. During the address phase of a transaction, CBE[3:0]# define
the bus command. During the data phase, CBE[3:0]# are used as Byte Enables.
Connect to PCI Bus: CBE[3:0]#.
Parity. Parity is even parity across AD[31:00] and CBE[3:0]#. The master drives PAR
for address and write data phases; the Bus Interface drives PAR for read data phases.
Connect to PCI Bus: PAR.
Cycle Frame. FRAME# is driven by the current master to indicate the beginning and
duration of an access. Connect to PCI Bus: FRAME#.
Initiator Ready. IRDY# is used to indicate the initiating agent’s (bus master’s) ability
to complete the current data phase of the transaction. IRDY# is used in conjunction
with TRDY#. Connect to PCI Bus: IRDY#.
Target Ready. TRDY# is used to indicate s the Bus Interface’s ability to complete the
current data phase of the transaction. TRDY# is used in conjunction with IRDY#.
Connect to PCI Bus: TRDY#.
Stop. STOP# is asserted to indicate the Bus Interface is requesting the master to stop
the current transaction. Connect to PCI Bus: STOP#.
Initialization Device. IDSEL input is used as a chip select during configuration read
and write transactions. Connect to PCI Bus: IDSEL.
Device Select. When actively driven, DEVSEL# indicates the driving device has
decoded its address as the target of the current access. As an input, DEVSEL#
indicates whether any device on the bus has been selected. Connect to PCI Bus:
DEVSEL#.
Request. REQ# is used to indicate to the arbiter that this agent desires use of the bus.
Connect to PCI Bus: REQ#.
Grant. GNT# is used to indicate to the agent that access to the bus has been granted.
Connect to PCI Bus: GNT#.
Parity Error. PERR# is used for the reporting of data parity errors. Connect to PCI
Bus: PERR#.
System Error. SERR# is an open drain output asserted to report address parity
errors, data parity errors on the Special Cycle command, or any other system error
where the result will be catastrophic. Connect to PCI Bus: SERR#.
Interrupt A. INTA# is an open drain output asserted to request an interrupt. Connect
to PCI Bus: INTA#.
Power Management Event. Active low open drain or active high TTL output (selected
by the PME DRV bit in the EEPROM) asserted when a valid ring signal is detected
and the PME_En bit of the PMCSR is a 1. This signal should be used only if the target
PCI Bus supports power management wake-up event. Connect to the PCI Bus: PME#.
(P9573-11 only.)
Status Changed. Active low output asserted to alert the host to changes in the
RRdy/-Bsy bit (PRR1) in the Pin Replacement Register (PRR) and to the setting of the
ReqAttn bit (ESR4) in the Extended Status Register (ESR). (P9573-12 only.)
3-8
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100475A
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