28F016S3 Ver la hoja de datos (PDF) - Intel
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28F016S3 Datasheet PDF : 41 Pages
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28F004S3/28F008S3/28F016S3
E
4.8 Program Suspend Command
The Program Suspend command allows program
interruption to read data in other flash memory
locations. Once the program process starts, writing
the Program Suspend command requests that the
WSM suspend the program sequence at a
predetermined point in the algorithm. The device
continues to output status register data when read
after the Program Suspend command is written.
Polling status register bits SR.7 and SR.2 can
determine when the program operation has been
suspended (both will be set to “1”). RY/BY# will also
transition to VOH. Specification tWHRH1 defines the
program suspend latency.
At this point, a Read Array command can be written
to read data from locations other than that which is
suspended. The only other valid commands while
program is suspended are Read Status Register
and Program Resume. After Program Resume
command is written to the flash memory, the WSM
will continue the program process. Status register
bits SR.2 and SR.7 will automatically clear and
RY/BY# will return to VOL. After the Program
Resume command is written, the device
automatically outputs status register data when
read (see Figure 10). VPP must remain at VPPH1/2
(the same VPP level used for program) while in
program suspend mode. RP# must also remain at
VIH or VHH (the same RP# level used for program).
4.9 Set Block and Master Lock-Bit
Commands
A flexible block locking and unlocking scheme is
enabled via a combination of block lock-bits and a
master lock-bit. The block lock-bits gate program
and erase operations while the master lock-bit
gates block-lock bit modification. With the master
lock-bit not set, individual block lock-bits can be set
using the Set Block Lock-Bit command. The Set
Master Lock-Bit command, in conjunction with
RP# = VHH, sets the master lock-bit. After the
master lock-bit is set, subsequent setting of block
lock-bits requires both the Set Block Lock-Bit
command and VHH on the RP# pin. See Table 5 for
a summary of hardware and software write
protection options.
Set block lock-bit and master lock-bit are initiated
using two-cycle command sequence. The set block
or master lock-bit setup along with appropriate
block or device address is written followed by either
the set block lock-bit confirm (and an address within
the block to be locked) or the set master lock-bit
confirm (and any device address). The WSM then
controls the set lock-bit algorithm. After the
sequence is written, the device automatically
outputs status register data when read (see
Figure 11). The CPU can detect the completion of
the set lock-bit event by analyzing the RY/BY# pin
output or status register bit SR.7.
When the set lock-bit operation is complete, status
register bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The
CUI will remain in read status register mode until a
new command is issued.
This two-step sequence of setup followed by
execution ensures that lock-bits are not accidentally
set. An invalid Set Block or Master Lock-Bit
command will result in status register bits SR.4 and
SR.5 being set to “1.” Also, reliable operations
occur only when VCC = VCC2 and VPP = VPPH1/2. In
the absence of this high voltage, lock-bit contents
are protected against alteration.
A successful set block lock-bit operation requires
that the master lock-bit be cleared or, if the master
lock-bit is set, that RP# = VHH. If it is attempted with
the master lock-bit set and RP# = VIH, the operation
will fail, and SR.1 and SR.4 will be set to “1.” A
successful set master lock-bit operation requires
that RP# = VHH. If it is attempted with RP# = VIH,
the operation will fail, and SR.1 and SR.4 will be set
to “1.” Set block and master lock-bit operations with
VIH < RP# < VHH produce spurious results and
should not be attempted.
18
PRELIMINARY
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