73K222BL
V.22, V.21, Bell 212A, Bell 103
Single-Chip Modem with Integrated Hybrid
TIMING DIAGRAMS
ALE
RD
WR
AD0-AD7
CS
TLL
TLC
TRW
TCL
TLC
TLA
TAL
ADDRESS
TRD
TRDF
READ DATA
ADDRESS
FIGURE 2: Bus Timing Diagram
TWW
TDW
TWD
WRITE
EXCLK
RD
A0-A2
TAC
TCA
ADDRESS
DATA
TRD
TCKD
D0
D1
D2
D3
D4
D5
D6
FIGURE 3: Read Timing Diagram (Serial Version)
TRDF
D7
EXCLK
WR
A0-A2
DATA
TWW
TDCK
D0
D1
D2
D3
D4
TCKW
TAC
TCA
ADDRESS
TWH
D5
D6
D7
FIGURE 4: Write Timing Diagram (Serial Version)
20