EDL1216CASA-10-E Ver la hoja de datos (PDF) - Elpida Memory, Inc

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EDL1216CASA-10-E

128M bits Mobile RAM

Elpida Memory, Inc 

EDL1216CASA

Initialization

The synchronous DRAM is initialized in the power-on sequence according to the following.

(1) To stabilize internal circuits, when power is applied, a 200 µs or longer pause must precede any signal toggling.

(2) After the pause, all banks must be precharged using the Precharge command (The Precharge all banks

command is convenient).

(3) Once the precharge is completed and the minimum tRP is satisfied, two or more Auto refresh must be performed.

(4) Both the mode register and the extended mode register must be programmed. After the mode register set cycle

or the extended mode register set cycle, tRSC (2 CLK minimum) pause must be satisfied.

Remarks:

1 The sequence of Auto refresh, mode register programming and extended mode register programming above may

be transposed.

2 CKE and DQM must be held high until the Precharge command is issued to ensure data-bus High-Z.

Programming Mode Registers

The mode register and extended mode register are programmed by the Mode register set command and Extended

mode register command, respectively using address bits A11 through A0, BA0 and BA1 as data inputs. The

registers retain data until they are re-programmed, or the device enters into the deep power down or the device

loses power.

Mode register

The mode register has three fields;

Options

: A11 through A7

/CAS latency : A6 through A4

Wrap type : A3

Burst length : A2 through A0

Following mode register programming, no command can be issued before at least 2 CLK have elapsed.

/CAS Latency

/CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse before

the data will be available. The value is determined by the frequency of the clock and the speed grade of the device.

Burst Length

Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is

completed, the output bus will become High-Z. The burst length is programmable as 1, 2, 4, 8 or full page.

Wrap Type (Burst Sequence)

The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either

“Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.

Some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing.

“Burst Length Sequence” shows the addressing sequence for each burst length using them. Both sequences

support bursts of 1, 2, 4 and 8. Additionally, sequence supports the full page length.

Data Sheet E0195E30 (Ver. 3.0)

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