RM5231-200-QI Ver la hoja de datos (PDF) - PMC-Sierra

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RM5231-200-QI

Microprocessor with 32-Bit System Bus

PMC-Sierra 

RM5231™ Microprocessor with 32-bit System Bus Data Sheet

Released

4. Write-through without write allocate

Loads and instruction fetches first search the cache, reading main memory only if the desired

data is not cache resident. On data store operations, the cache is first searched to determine if

the target address is cache resident. If it is resident, the cache contents are updated and main

memory is written, leaving the write-back bit of the cache line unchanged. If the cache lookup

misses, then only main memory is written.

The most commonly used write policy is write-back, where a store to a cache line does not

immediately cause the main memory to be updated. This increases system performance by

reducing bus traffic and eliminating the bottleneck of waiting for each store operation to finish

before issuing a subsequent memory operation. Software can, however, select write-through on a

per-page basis when appropriate, such as for frame buffers.

Associated with the data cache is the store buffer. When the RM5231 executes a store instruction,

this single-entry buffer gets written with the store data while the tag comparison is performed. If

the tag matches, then the data is written into the data cache in the next cycle that the data cache is

not accessed (the next non-load cycle). The store buffer allows the RM5231 to execute a store

every processor cycle and to perform back-to-back stores without penalty. In the event of a store

immediately followed by a load to the same address, a combined merge and cache write occurs

such that no penalty is incurred.

The RM5231 cache attributes for both the instruction and data caches are summarized in Table 3.

Table 3 Cache Attributes

Characteristics Instruction

Size

32 KB

Organization

2-way set

associative

Line size

32 B

Index

vAddr11..0

Tag

pAddr31..12

Write policy

n.a.

Read order

write order

miss restart after

transfer of

Parity

Cache locking

sub-block

sequential

entire line

per-word

set A

Data

32 KB

2-way set

associative

32 B

vAddr11..0

pAddr31..12

write-back/write-

through

sub-block

sequential

first double

per-byte

set A

3.20 Write Buffer

Writes to external memory, whether cache miss write-backs or stores to uncached or write-through

addresses, use the on-chip write buffer. The write buffer holds up to four 64-bit address and data

pairs. The entire buffer is used for a data cache write-back and allows the processor to proceed in

parallel with the memory update. For uncached and write-through stores, the write buffer

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

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Document ID: PMC-2002165, Issue 1

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