ADM1024(2000) Ver la hoja de datos (PDF) - Analog Devices
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ADM1024 Datasheet PDF : 28 Pages
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ADM1024
to be asserted. After masking, the status bits are all OR’d
together to produce the INT output, which will pull low if any
unmasked status bit goes high, i.e., when any measured value
goes out of limit. The ADM1024 also has a dedicated output for
temperature interrupts only, the THERM input/output Pin 2.
The function of this is described later.
The INT output is enabled when Bit 1 of Configuration Register 1
(INT_Enable) is high, and Bit 3 (INT_Clear) is low.
The INT pin has an internal, 100 kΩ pull-up resistor.
VID/IRQ INPUTS
The processor voltage ID inputs VID0 to VID4 can be reconfig-
ured as interrupt inputs by setting Bit 7 of the Channel Mode
Register (address 16h). In this mode they operate as level-triggered
interrupt inputs, with VID0/IRQ0 to VID2/IRQ2 being active
low and VID2/IRQ2 and VID4/IRQ4 being active high. The
individual interrupt inputs can be enabled or masked by setting
or clearing Bits 4 to 6 of the Channel Mode Register and Bits
6 and 7 of Configuration Register 2 (address 4Ah). These interrupt
inputs are not latched in the ADM1024, so they do not require
clearing as do bits in the Status Registers. However, the external
interrupt source should be cleared once the interrupt has been
serviced, or the interrupt request will be reasserted.
INTERRUPT CLEARING
Reading an Interrupt Status Register will output the contents of
the Register, then clear it. It will remain cleared until the moni-
toring cycle updates it, so the next read operation should not be
performed on the register until this has happened, or the result
will be invalid. The time taken for a complete monitoring cycle
is mainly dependent on the time taken to measure the fan speeds,
as described earlier.
The INT output is cleared with the INT_Clear bit, which is Bit
3 of the Configuration Register, without affecting the contents
of the Interrupt (INT) Status Registers.
VID0/IRQ0
VID1/IRQ1
VID2/IRQ2
VID3/IRQ3
VID4/IRQ4
VID0–VID4
REGISTERS
4
5
CHANNEL
MODE
REGISTER
6
7
6
CONFIGURATION
REGISTER 2
7
FROM
VALUE
AND LIMIT
REGISTERS
HIGH
LIMIT
VALUE
LOW
LIMIT
HIGH
AND
LOW
LIMIT
COMPARA-
TORS
1 = OUT
OF
LIMIT
DATA
DEMULTI-
PLEXER
2.5V/EXT.
TEMP 2
VCCP1
VCC
+5V
INT. TEMP
EXT. TEMP1
FAN1/AIN1
FAN2/AIN2
+12V
VCCP2
RESERVED
RESERVED
CI
THERM
D1 FAULT
D2 FAULT
0
1
2
3
INTERRUPT
STATUS
4 REGISTER 1
5
6
7
0
1
2
3
INTERRUPT
STATUS
4 REGISTER 2
5
6
7
16 MASK BITS
MASKING
DATA
FROM BUS
INTERRUPT MASK
REGISTERS 1 AND 2
(SAME BIT ORDER AS
STATUS REGISTERS)
MASK GATING ؋ 11
STATUS
BIT
MASK
BIT
INT
INT ENABLE
INT CLEAR
CONFIGURATION
REGISTER 1
THERM
THERM
CLEAR
THERM
Figure 21. Interrupt Register Structure
–18–
REV. 0
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