M38861F3FS Ver la hoja de datos (PDF) - MITSUBISHI ELECTRIC
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M38861F3FS Datasheet PDF : 110 Pages
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MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction reg-
ister corresponds to one pin, and each pin can be set to be input
port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
When the P8 function select bit of the port control register 2 (ad-
dress 002F16) is set to “1”, read from address 001016 becomes
the port P4 input register, and read from address 001116 becomes
the port P7 input register.
As the particular function, value of P42 to P46 pins and P70 to P75
pins can be read regardless of setting direction registers, by read-
ing the port P4 input register (address 001016) or the port P7 input
register (address 001116) respectively.
Table 4 I/O port function (1)
Pin
Name
P00/P3REF
P01–P07
P10–P17
P20–P27
P30/PWM00
P31/PWM10
P32–P37
P40/XCOUT
P41/XCIN
P42/INT0/
OBF00
P43/INT1/
OBF01
P44/RXD
Port P0
Port P1
Port P2
Port P3
P45/TXD
P46/SCLK1
/OBF10
Port P4
P47/SRDY1
/S1
Input/Output
I/O Structure
CMOS compatible
input level
CMOS 3-state output
or N-channel open-
drain output
CMOS compatible
input level
CMOS 3-state output
Input/output,
individual bits
CMOS compatible
input level or TTL
input level
CMOS 3-state output
or N-channel open-
drain output
CMOS compatible
input level
CMOS 3-state output
(when selecting bus
interface function)
CMOS compatible
input level or TTL
input level
Non-Port Function
Address low-order byte
output
Analog comparator
power source input pin
Related SFRs
CPU mode register
Port control register 1
Serial I/O2 control
register
Address low-order byte
output
Address high-order
byte output
Data bus I/O
Control signal I/O
PWM output
Key-on wake up input
Comparator input
Control signal I/O
Key-on wake up input
Comparator input
Sub-clock generating
circuit
CPU mode register
Port control register 1
CPU mode register
CPU mode register
Port control register 1
AD/DA control register
CPU mode register
Port control register 1
CPU mode register
External interrupt input Interrupt edge selection
Bus interface function register
I/O
Port control register 2
Serial I/O1 function in-
put
Serial I/O1 function out-
put
Serial I/O1 function I/O
Bus interface function
output
Serial I/O1 control
register
Port control register 2
Serial I/O1 control
register
UART control register
Port control register 2
Serial I/O1 control
register
Data bus buffer control
register
Port control register 2
Serial I/O1 function out-
put
Bus interface function
input
Serial I/O1 control
register
Data bus buffer control
register
Ref.No.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
12
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