UT1750AR12WCC(2003) Ver la hoja de datos (PDF) - Aeroflex UTMC

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UT1750AR12WCC
(Rev.:2003)

RadHard RISC Microprocessor

Aeroflex UTMC 

The RISC Instruction Counter Register (IC) and The RISC

Instruction Register (IR)

The UT1750AR’s RISC interface consists of a 20-bit instruction

address and a 16-bit data bus. The RISC Instruction Counter

Register (IC) supplies the 20-bit address to RISC memory. The

RISC’s instruction data that is read from memory is then input

into the RISC’s Instruction Register (IR). The IR consists of two

sets of latches, a Primary Instruction Register latch (PIR) and

the Instruction Register latch (IRL). These two sets of latches

allow the UT1750AR to perform overlapping memory fetch and

execute cycles. This means the UT1750AR performs a delayed

branch when the flow of the program is interrupted. A delayed

branch implies that the UT1750AR fetches and executes the

instruction following the branch condition BEFORE the

UT1750AR executes the first instruction at the branch location.

19 18 17 16 15 14 13 121110 9 8 7 6 5 4 3 2 1 0

I I III II III III II IIIII

C C CCC CC CCC CCC C C CCCCC

1 1 111 11 111 987 65 43210

9 8 765 43 210

MSB

LSB

Figure 18. RISC Instruction Counter Register (IC)

The RISC Instruction Register (IR) is made of two 16-bit

latches: the Primary Instruction Register (PIR) latch, and the

Instruction Register (IRL) latch.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

I I I II II III I IIIII

R R R RR RR RRR R RRRRR

1 1 1 11 19 8 76 54 3210

5 43210

MSB

LSB

Figure 19. Instruction Register (IR)

The RISC Instruction Counter Save Register (ICS)

The UT1750AR uses the RISC’s Instruction Counter Save

Register (ICS) (figure 20) when servicing interrupts and branch

instructions. When an interrupt or branch occurs, the

UT1750AR saves the IC in the ICS. Read the ICS

IMMEDIATELY after entering the target routine so the return

location can be stored before any other IC saves. The

UT1750AR reads the ICS using the RISC Input instruction. The

configuration of the ICS is shown below.

19 18 17 16 15 14 13 121110 9 8 7 6 5 4 3 2 1 0

I I II I I I I I I I I I I I I I II I

C C CC C C C C C C C CC C C C C C C C

S S SS S S S S S S S SS S S S S S S S

1 1 111 11 111 987 65 4 3210

9 8 765 43 2 10

MSB

LSB

Figure 20. RISC Instruction Counter Save

Register (ICS)

Pipe Register (PIPE)

The PIPE Register (figure 21) holds the pre-fetched MIL-STD-

1750A instruction. The UT1750AR reads the PIPE Register

with the RISC I/O instruction.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

P P PP PP PP PPP PPP PP

I I III II II II II III

P PP PP PP PP PP PP PPP

E EE EE EE EE EE EE EEE

1 1 1 11 19 87 65 432 10

5 4 3210

MSB

LSB

Figure 21. The PIPE Register (PIPE)

Program Register (PR)

The Program Register holds the present MIL-STD-1750A

instruction. Figure 22 shows the configuration of the Program

Register (PR).

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

P P P PP PP PPP P PPPPP

R R RR RR R RRR R RRR RR

1 1 1 111 9 876 5 432 10

54

MSB

3 210

Opcode

IRS

IRD

LSB

Figure 22. Program Register (PR)

19

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