GS7000 Ver la hoja de datos (PDF) - Gennum -> Semtech
Número de pieza
componentes Descripción
Fabricante
GS7000 Datasheet PDF : 14 Pages
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The figure below describes the relationship between the input parallel clock and the input parallel data. The input parallel
data must be stable for 4ns prior to the rising edge of the PCLKIN (setup time), and for 4 ns following the rising edge of the
PCLKIN (hold time).
tSETUP = 4ns
tHOLD = 4ns
DIN(n)
PCLKIN
Fig. 22 Transmitter Setup and Hold Time
TYPICAL APPLICATION CIRCUITS
100n
VCC1 GND
10u
VCC
100p
VCC
10n
10n 75
10n 75
75
VCC
37.5
10n
All resistors in ohms,
all capacitors in farads,
unless otherwise shown.
AGC
AGC
GND TRISTATE
VCC
DIN
DIN
GND
CD
DOUT
DOUT
CD-ADJ
VCC
OEM
GS9024
VCC
10n
75
1u
10n
SSI-CD
13 12 11 10 9 8 7 6 5 4 3 2 1
10n
14 NC
VCC
75 75
100n
15 VEE1
16 C1
100n
17 C2
18 VCC1
19 SDI
VCC
VCC
100n
475
VCC
2k
VCC
20 SDI
21
22
23
VCC2
PCLKIN
24 VEE2
EQ
25
Rx/Tx
26
NC
GS7000
NC 52
VEE3 51
SDO 50
SDO 49
VCC3
CD
48
47
SMPTE 46
45
NC
44
NC
43
PCLKOUT 42
VDD 41
VSS 40
NC
475
220
LOCK
27 28 29 30 31 32 33 34 35 36 37 38 39
10k
PARALLEL DATA OUTPUTS
VCC
VCC
220
100n
CD
10k
VCC
MODE
33 PCLK OUT
VCC
10p
100n
Typical Receiver Application Circuit with External Equalizer
11
522 - 06 - 02
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