Continued from preceding page
Pin number Pin name
6
CLKIN
7
CLKOUT
LB1875
VREG
Equivalent circuit
30 kΩ
5.6 KΩ
6
Pin function
Clock input (max. 10 kHz)
Low: 0 to 1.5V
High: 3.5V to V
REG
High when open.
VREG
A11354
7
Quartz oscillator divider output
Ratio is selected with pin 5.
Open collector output
8
F/R
9
FGSEL
10
LIM
VREG
VREG
VREG
A11355
30 kΩ
5.6 kΩ
8
A11356
30 kΩ
5.6 kΩ
9
A11357
30 kΩ
5.6 kΩ
10
A11358
Forward/reverse switching pin
Low: 0 to 1.5V
High: 3.5V to VREG
High when open.
FG comparator selector pin
Low: 0 to 1.5V
–> Speed control on FG single edge
High: 3.5V to V
REG
–> Speed control on FG dual edge
High when open.
Drive mode selector pin
Low: 0 to 1.5V
–> Direct PWM drive mode
High: 3.5 V to VREG
–> PAM drive mode
High when open.
Continued on next page
No. 6002-13/17