W83629D Ver la hoja de datos (PDF) - Winbond

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componentes Descripción

Fabricante

W83629D

PCI TO ISA BRIDGE SET

Winbond 

W83628F & W83629D

Bit 3

Bit 2

Bit 1

Bit 0

Parity Error Response(Not supported).

Hardwired to zero.

Bus Master Enable.

Hardwired to one. The ISA bridge Bus Masters are always supported to generate a

PCI Bus master cycle.

Memory Space Enable.

Hardwired to one. The ISA bridge Memory space is always enabled.

I/O Space Enable.

Hardwired to one. The ISA bridge I/O space is always enabled.

8.4 PCISTS-PCI STATUS REGISTER

Address Offset:

06-07h

Default Value:

0200h

Attribute:

Read/Write

This register shows status information for PCI bus related events.

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10:9

Bit 8

Bit 7

Detected Parity Error.

Hardwired to zero. The ISA bridge does not check bus parity.

Signaled System Error.

This bit is set when ISA bridge asserts SERR# on PCI bus.

Received Master Abort Status.

This bit is set when the ISA bridge is target aborted as a master on the PCI bus.

Software sets this bit to 0 by writing a 1 to it.

Received Target Abort Status.

This bit is set when the ISA bridge target aborts a PCI transaction as a target.

Software sets this bit to 0 by writing a 1 to it.

Signaled Target Abort Status.

This bit is set when the ISA bridge signals a target abort for a PCI transaction.

Software sets this bit to 0 by writing a 1 to it.

DEVSEL# Timing. This 2 bits always return a 01b(medium decode).

Data Parity Detected(Not supported).

Hardwired to zero.

Fast Back-to-Back(Not supported).

Hardwired to zero.

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Publication Release Date: May 18, 2005

Revision A1

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