LC72P366 Ver la hoja de datos (PDF) - SANYO -> Panasonic

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LC72P366

On-Chip One-Time Programmable PROM Single-Chip PLL Controller

SANYO -> Panasonic 

LC72P366

Continued from preceding page.

Mnemonic

AND

ANDI

OR

ORI

EXL

EXLI

SHR

LD

ST

MVRD

MVRS

MVSR

MVI

TMT

TMF

JMP

CAL

RT

RTS

RTB

RTBS

RTI

SS

RS

TST

TSF

TUL

PLL

INR

OUTR

Operand

1st 2n

rM

MI

rM

MI

rM

MI

r

rM

Mr

rM

Mr

M1 M2

MI

MN

MN

ADDR

ADDR

IN

IN

IN

IN

N

Mr

M Rn

M Rn

Function

Operation

D15 14 13 12 11 10

AND M with r

r ← (r) AND (M)

001000

AND I with M

M ← (M) AND I

001001

OR M with r

r ← (r) OR (M)

001010

OR I with M

M ← (M) OR I

001011

Exclusive OR I with r r ← (r) XOR I

001101

Exclusive OR I with M M ← (M) XOR I

001101

Shift r right with carry

carry

(r)

000000

Load M to r

r ← (M)

110100

Store r to M

M ← (r)

110101

Move M to destinsation [DH, rn] ← (M)

M referring to r in

the same row

110110

Move M to destinsation M ← [DH, rn]

M referring to r in

the same row

110111

Move source M referring [DH, DL1] ← [DH, DL2] 1 1 1 0 0 0

to r to M in the same row

Move I to M

M←I

111001

Test M bits, then skip

if all bits specified

are true

if M (N) = all “1”,

then skip

111100

Test M bits, then skip

if all bits specified

are false

if M (N) = all “0”,

then skip

111101

Jump to the address PC ← ADDR

10

Call subroutine

Stack ← (PC) + 1

1100

Return from subroutine PC ← Stack

000000

Return from subroutine PC ← Stack + 1

and skip

000000

Return from subroutine PC ← Stack

with bank data

BANK ← Stack

111111

Return from subroutine PC ← Stack + 1

with bank data and skip BANK ← Stack

111111

Return from interrupt

PC ← Stack

BANK ← Stack

CARRY ← Stack

000000

Set status register

(Status reg I) N ← 1

111111

Reset status register (Status reg I) N ← 0

111111

Test status register

true

if (Status reg I) N =

all “1”, then skip

111111

Test status register

false

if (Status reg I) N =

“0”, then skip

111111

Test unlock F/F then

skip if it has not been

set

if Unlock FF (N) =

all “0”, then skip

000000

Load M to PLL register PLL reg ← PLL data

111110

Input register/port

data to M

M ← (Rn reg)

001110

Output contents of M

to register/port

Rn reg ← (M)

001111

Machine code

9 8 7 6 5 4 3 2 1 D0

DH

DL

r

DH

DL

I

DH

DL

r

DH

DL

r

DH

DL

r

DH

DL

I

001110

r

DH

DL

r

DH

DL

r

DH

DL

r

DH

DL

r

DH

DL1

DL2

DH

DL

I

DH

DL

N

DH

DL

N

ADDR (14 bits)

ADDR (12 bits)

001000

001010

111100

111101

001001

11000 I

N

11001 I

N

1101

I

N

1110

I

N

001101

N

DH

DL

r

DH

DL

Rn

DH

DL

Rn

Continued on next page.

No. 5544-13/14

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