MAQ28139FD Ver la hoja de datos (PDF) - Dynex Semiconductor

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componentes Descripción

Fabricante

MAQ28139FD

OBDH Bus Terminal

Dynex Semiconductor 

MA28139

Bit Position

RIRSYNC

RIRCLK

RIRDATA

RIRVAL

IRCLK

TRCLK

CTCLK

CHADD(0:7)

MODS16

DIGIN

DATARRT

ENRRT

Bit Position

RIRSYNC

RIRCLK

RIRDATA

RIRVAL

IRCLK

TRCLK

CTCLK

CHADD(0:7)

MODS16

DIGIN

DATARRT

ENRRT

Note 1: One 16-bit Digital Serial Acquisition command takes 2 Interrogations to complete. A succeeding Acquisition or Switch

Closure command of any type is hence not possible and forms a protocol violation. The second command of such a sequence

will be rejected.

Note 2: For any acquisition command to be decoded, the evaluated Memory Load Address must be zero. An evaluated Memory Load

Address of non-zero does not imply data acquisition.

Note 3: The Memory Load Address which is evaluated for decoding and addressing usage may vary from 3 to 5 bits.

If (EXTMLA1 = 1) and (EXTMLA2 = 0), the Memory Load Address field is extended to 4 bits and bit 11 of the Interrogation will be

treated as MLA(1).

If (EXTMLA2 = 1), the Memory Load Address field is extended to 5 bits and bits 10 and 11 of the Interrogation will be

treated as MLA(0:1).

Any Interrogation bits treated as Extended Memory Load Address bits will not be treated as Terminal Address bits; this facility is

intended for 2x or 4x size expansion provided that up to 4 consecutive Terminal Addresses can be used.

Note 4: The 16-bit Digital Serial Acquisition command response is always 21 bits in length; the Destination Address is simply

copied from the Interrogation into the Response.

Figure 15: 16-Bit Digital Serial Acquisition Waveforms

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