Multimedia ICs
1) Input clocks and input data timings in the various
operation modes
There are slight differences in the input data and the clock
timing, depending on which mode is being used. What is
shared by all modes is that, with the BU1425AK / AKV,
BU1425AK / BU1425AKV
data is read and discharged at the rising edge of the
internal clock. The illustration below shows the input con-
ditions in the various modes.
1. Master mode, ∗1 clock mode
Encoder master (pin 33 = H)
Internal clock = input clock (pin 53 = H)
VCLK (pin53)
Internal clock (BCLK)
Input data
Output data (HSY, VSY)
Tds1
Fig.11
∗ In this mode, the internal clock (BCLK) begins to operate at the same phase as the VCLK input, following the rise
of the RSTB pin (pin 52).
Table 11
Parameter
Data setup time 1
Symbol
Min.
Typ.
Max.
Tds1
10
—
—
18