13.2
13.3
13.4
13.5
13.6
13.7
13.1.32 FWH_DEC_EN1âFirmware Hub Decode Enable
Register (LPC I/FâD31:F0) ................................................................ 487
13.1.33 BIOS_CNTLâBIOS Control Register
(LPC I/FâD31:F0)............................................................................. 489
13.1.34 FDCAPâFeature Detection Capability ID
Register (LPC I/FâD31:F0)................................................................ 490
13.1.35 FDLENâFeature Detection Capability Length
Register (LPC I/FâD31:F0)................................................................ 490
13.1.36 FDVERâFeature Detection Version
Register (LPC I/FâD31:F0)................................................................ 490
13.1.37 FDVCTâFeature Vector Register
(LPC I/FâD31:F0)............................................................................. 491
13.1.38 RCBAâRoot Complex Base Address Register
(LPC I/FâD31:F0)............................................................................. 491
DMA I/O Registers........................................................................................... 492
13.2.1 DMABASE_CAâDMA Base and Current Address Registers ....................... 493
13.2.2 DMABASE_CCâDMA Base and Current Count Registers .......................... 494
13.2.3 DMAMEM_LPâDMA Memory Low Page Registers.................................... 494
13.2.4 DMACMDâDMA Command Register ..................................................... 495
13.2.5 DMASTAâDMA Status Register ........................................................... 495
13.2.6 DMA_WRSMSKâDMA Write Single Mask Register .................................. 496
13.2.7 DMACH_MODEâDMA Channel Mode Register ........................................ 497
13.2.8 DMA Clear Byte Pointer Register.......................................................... 498
13.2.9 DMA Master Clear Register ................................................................. 498
13.2.10 DMA_CLMSKâDMA Clear Mask Register ............................................... 498
13.2.11 DMA_WRMSKâDMA Write All Mask Register ......................................... 499
Timer I/O Registers ......................................................................................... 499
13.3.1 TCWâTimer Control Word Register...................................................... 500
13.3.2 SBYTE_FMTâInterval Timer Status Byte Format Register ....................... 502
13.3.3 Counter Access Ports Register ............................................................. 503
8259 Interrupt Controller (PIC) Registers ........................................................... 503
13.4.1 Interrupt Controller I/O MAP ............................................................... 503
13.4.2 ICW1âInitialization Command Word 1 Register..................................... 504
13.4.3 ICW2âInitialization Command Word 2 Register..................................... 505
13.4.4 ICW3âMaster Controller Initialization Command
Word 3 Register ................................................................................ 505
13.4.5 ICW3âSlave Controller Initialization Command
Word 3 Register ................................................................................ 506
13.4.6 ICW4âInitialization Command Word 4 Register..................................... 506
13.4.7 OCW1âOperational Control Word 1 (Interrupt Mask)
Register ........................................................................................... 507
13.4.8 OCW2âOperational Control Word 2 Register ......................................... 507
13.4.9 OCW3âOperational Control Word 3 Register ......................................... 508
13.4.10 ELCR1âMaster Controller Edge/Level Triggered Register ........................ 509
13.4.11 ELCR2âSlave Controller Edge/Level Triggered Register .......................... 510
Advanced Programmable Interrupt Controller (APIC)............................................ 511
13.5.1 APIC Register Map............................................................................. 511
13.5.2 INDâIndex Register .......................................................................... 511
13.5.3 DATâData Register ........................................................................... 512
13.5.4 EOIRâEOI Register ........................................................................... 512
13.5.5 IDâIdentification Register .................................................................. 513
13.5.6 VERâVersion Register ....................................................................... 513
13.5.7 REDIR_TBLâRedirection Table ............................................................ 514
Real Time Clock Registers................................................................................. 516
13.6.1 I/O Register Address Map ................................................................... 516
13.6.2 Indexed Registers ............................................................................. 517
13.6.2.1 RTC_REGAâRegister A ........................................................ 518
13.6.2.2 RTC_REGBâRegister B (General Configuration)....................... 519
13.6.2.3 RTC_REGCâRegister C (Flag Register) ................................... 520
13.6.2.4 RTC_REGDâRegister D (Flag Register) .................................. 520
Processor Interface Registers ............................................................................ 521
13.7.1 NMI_SCâNMI Status and Control Register............................................ 521
13.7.2 NMI_ENâNMI Enable (and Real Time Clock Index)
Register ........................................................................................... 522
13.7.3 PORT92âFast A20 and Init Register .................................................... 522
13.7.4 COPROC_ERRâCoprocessor Error Register ........................................... 522
13.7.5 RST_CNTâReset Control Register........................................................ 523
Datasheet
13