5.27.2
5.27.3
5.27.4
5.27.5
IntelÂź VT-d Features Supported.......................................................... 276
Support for Function Level Reset (FLR) in PCH ...................................... 277
Virtualization Support for PCHâs IOxAPIC .............................................. 277
Virtualization Support for High Precision Event Timer (HPET) .................. 277
6 Ballout Definition................................................................................................... 279
6.1 Desktop PCH Ballout ........................................................................................ 279
6.2 Mobile PCH Ballout .......................................................................................... 290
6.3 Mobile SFF PCH Ballout .................................................................................... 302
7 Package Information ............................................................................................. 307
7.1 Desktop PCH package ...................................................................................... 307
7.2 Mobile PCH Package......................................................................................... 309
7.3 Mobile SFF PCH Package................................................................................... 311
8 Electrical Characteristics ....................................................................................... 313
8.1 Thermal Specifications ..................................................................................... 313
8.1.1
Desktop Storage Specifications and Thermal Design Power (TDP) ............ 313
8.1.2
Mobile Storage Specifications and Thermal Design Power (TDP) .............. 313
8.2 Absolute Maximum Ratings............................................................................... 314
8.3 PCH Power Supply Range ................................................................................. 315
8.4 General DC Characteristics ............................................................................... 315
8.5 Display DC Characteristics ................................................................................ 328
8.6 AC Characteristics ........................................................................................... 330
8.7 Power Sequencing and Reset Signal Timings ....................................................... 347
8.8 Power Management Timing Diagrams................................................................. 350
8.9 AC Timing Diagrams ........................................................................................ 355
9 Register and Memory Mapping............................................................................... 365
9.1 PCI Devices and Functions................................................................................ 366
9.2 PCI Configuration Map ..................................................................................... 367
9.3 I/O Map ......................................................................................................... 367
9.3.1
Fixed I/O Address Ranges .................................................................. 367
9.3.2
Variable I/O Decode Ranges ............................................................... 370
9.4 Memory Map................................................................................................... 371
9.4.1
Boot-Block Update Scheme ................................................................ 373
10 Chipset Configuration Registers............................................................................. 375
10.1 Chipset Configuration Registers (Memory Space) ................................................. 375
10.1.1 CIR0âChipset Initialization Register 0 ................................................. 377
10.1.2 RPCâRoot Port Configuration Register ................................................. 377
10.1.3 RPFNâRoot Port Function Number and Hide for PCI
Express* Root Ports Register .............................................................. 378
10.1.4 FLRSTATâFunction Level Reset Pending Status Register ........................ 379
10.1.5 TRSRâTrap Status Register ............................................................... 380
10.1.6 TRCRâTrapped Cycle Register ............................................................ 380
10.1.7 TWDRâTrapped Write Data Register ................................................... 381
10.1.8 IOTRnâI/O Trap Register (0â3).......................................................... 381
10.1.9 V0CTLâVirtual Channel 0 Resource Control Register.............................. 382
10.1.10 V0STSâVirtual Channel 0 Resource Status Register............................... 382
10.1.11 V1CTLâVirtual Channel 1 Resource Control Register.............................. 383
10.1.12 V1STSâVirtual Channel 1 Resource Status Register............................... 383
10.1.13 RECâRoot Error Command Register .................................................... 384
10.1.14 LCAPâLink Capabilities Register ......................................................... 384
10.1.15 LCTLâLink Control Register................................................................ 385
10.1.16 LSTSâLink Status Register ................................................................ 385
10.1.17 DLCTL2âDMI Link Control 2 Register .................................................. 385
10.1.18 DMICâDMI Control Register ............................................................... 386
10.1.19 TCTLâTCO Configuration Register....................................................... 386
10.1.20 D31IPâDevice 31 Interrupt Pin Register .............................................. 387
10.1.21 D30IPâDevice 30 Interrupt Pin Register .............................................. 388
10.1.22 D29IPâDevice 29 Interrupt Pin Register .............................................. 388
10.1.23 D28IPâDevice 28 Interrupt Pin Register .............................................. 388
10.1.24 D27IPâDevice 27 Interrupt Pin Register .............................................. 390
10.1.25 D26IPâDevice 26 Interrupt Pin Register .............................................. 390
10.1.26 D25IPâDevice 25 Interrupt Pin Register .............................................. 390
10.1.27 D22IPâDevice 22 Interrupt Pin Register .............................................. 391
10.1.28 D31IRâDevice 31 Interrupt Route Register .......................................... 392
Datasheet
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