Philips Semiconductors
Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)
Preliminary specification
TDA1305T
QUALITY SPECIFICATION
In accordance with “SNW-FQ-611E”. The number of this quality specification can be found in the “Quality Reference
Handbook”. The handbook can be ordered using the code 9398 510 63011.
DIGITAL CHARACTERISTICS
VDD = 3.4 to 5.5 V; VSS = 0 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDDD
digital supply voltage
note 1
3.4
5.0
5.5
V
IDDD
digital supply current
VDDD = 5 V;
−
at code 00000H
30
40
mA
VDDA
analog supply voltage
note 1
3.4
5.0
5.5
V
IDDA
analog supply current
VDDA = 5 V;
−
5.5
8
mA
at code 00000H
VDDO
operational amplifier supply note 1
voltage
3.4
5.0
5.5
V
IDDO
operational amplifier supply VDDO = 5 V;
−
6.5
9
mA
current
at code 00000H
RR
ripple rejection to VDDA
note 2
−
25
−
dB
System clock input
fsys
system frequency
fsys = 384fs
fsys = 256fs
VIL
LOW level input voltage
note 3
VIH
HIGH level input voltage
note 3
ILI
input leakage current
note 4
Ci
input capacitance
Tcy
clock cycle time
fsys = 384fs
fsys = 256fs
9.6
6.4
−0.5
0.8VDD
−
−
104
156
16.93
11.29
−
−
−
−
59.1
88.6
18.4
12.28
0.2VDD
VDD + 0.5
10
10
54.2
81.3
MHz
MHz
V
V
µA
pF
ns
ns
Digital inputs; WS, BCK, DATA, DSMB, MUSB, DEEM1, DEEM2, ATSB, CLKS1, CLKS2, TEST1 and TEST2
VIL
LOW level input voltage
note 3
VIH
HIGH level input voltage
note 3
ILI
input leakage current
note 4
Ci
input capacitance
−0.5
−
0.7VDD
−
−
−
−
−
0.3VDD V
VDD + 0.5 V
10
µA
10
pF
Digital output; CDEC
VOL
LOW level output voltage IOL = 0.4 mA
VOH
HIGH level output voltage IOH = −0.2 mA
tr
output rise time
note 5
tf
output fall time
note 5
CL
load capacitance
0
−
VDD − 0.5 −
−
−
−
−
−
−
0.5
V
VDD
V
20
ns
20
ns
30
pF
1995 Dec 08
10