TC7129
FIGURE 4-9:
ACCURACY ERRORS IN DUAL SLOPE CONVERSION
Integrate
De-integrate
Time
Over shoot due to zero crossing between
clock pulses
Integrator Residue Voltage
Clock Pulses
Over shoot caused by comparator
delay of 1 clock pulse
FIGURE 4-10:
Zero Integrate
and Latch
INTEGRATION WAVEFORM
INT1
Integrate
DE1
De-integrate REST X10 DE2 REST X10 DE3
Zero Integrate
TC7129
Integrator
Note: Shaded area greatly expanded in time and amplitude.
Residual Voltage
DS21459B-page 12
© 2002 Microchip Technology Inc.