NJU6434
! FUNCTIONAL DESCRIPTION
(1) Operation of each block
(1-1) Oscillation Circuit
The oscillation circuit operates by connecting external resistance (capacitance is incorporated).
This circuit provides the clock signal to both common and segment drivers.
(1-2) Divider Circuit
This circuit divides the oscillating signal to generate the common and segment timing.
(1-3) Shift-Register
When the CE terminal is "H" (Enable mode), the display data is transferred to the shift-register
synchronized by the shift clock on the SCL terminal.
(1-4) Latch Circuit and Segment Driver
When the CE signal falling, the display data is latched, and the data controls the segment signal of
display-on/off.
(1-5) Common Driver
The Common driver generates driving waveform to common terminal.
(1-6) Reset Circuit
The Reset circuit is type of detectable voltage. It resets internal circuit when the power turns on.
(1-7) LCD Driving Voltage Generator Circuit
The LCD Driving voltage generator circuit generates the LCD bias voltage. (Refer to “(6) LCD Panel
Drive” for details.)
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Ver.2009-11-12