MC10E1651
5V, -5VĄECL Dual ECL
Output Comparator with
Latch
The MC10E1651 is fabricated using ON Semiconductor’s advanced
MOSAIC IIIt process. The MC10E1651 incorporates a fixed level of
input hysteresis as well as output compatibility with 10 KH logic
devices. In addition, a latch is available allowing a sample and hold
function to be performed. The device is available in both a 16-pin DIP
and a 20-pin surface mount package.
The latch enable (LENa and LENb) input pins operate from standard
ECL 10 KH logic levels. When the latch enable is at a logic high level,
the MC10E1651 acts as a comparator; hence, Q will be at a logic high
level if V1 > V2 (V1 is more positive than V2). Q is the complement
of Q. When the latch enable input goes to a low logic level, the outputs
are latched in their present state providing the latch enable setup and
hold time constraints are met.
The 100 series contains temperature compensation.
• Typical 3.0 dB Bandwidth > 1.0 GHz
• Typical V to Q Propagation Delay of 775 ps
• Typical Output Rise/Fall of 350 ps
• Common Mode Range –2.0 V to +3.0 V
• Individual Latch Enables
• Differential Outputs
• 28mV Input Hysteresis
• Operating Mode: VCC= 5.0 V, VEE= –5.2 V
• No Internal Input Pulldown Resistors
• ESD Protection: > 2 KV HBM, > 100 V MM
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 85 devices
http://onsemi.com
CDIP–16
L SUFFIX
CASE 620
MARKING
DIAGRAMS
16
MC10E1651L
AWLYYWW
1
1 20
PLCC–20
FN SUFFIX
CASE 775
AWLYYWW
1651FN
MC10E
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC10E1651L
CDIP–16 25 Units/Rail
MC10E1651FN
PLCC–20 46 Units/Rail
MC10E1651FNR2 PLCC–20 500 Units/Reel
© Semiconductor Components Industries, LLC, 2002
1
April, 2002 – Rev. 5
Publication Order Number:
MC10E1651/D