M36W0R5020T0, M36W0R5020B0
FUNCTIONAL DESCRIPTION
The Flash memory and SRAM components have
separate power supplies but share the same
grounds. They are distinguished by three Chip En-
able inputs: EF for the Flash memory and E1S and
E2S for the SRAM.
Recommended operating conditions do not allow
more than one device to be active at a time. The
most common example is simultaneous read oper-
ations on the Flash memory and SRAM compo-
nents which would result in a data bus contention.
Therefore it is recommended to put the other de-
vices in the high impedance state when reading
the selected device.
Figure 4. Functional Block Diagram
VDDF VPPF VDDQ
A18-A20
A0-A17
EF
GF
WF
LF
KF
RPF
WPF
32 Mbit
Flash
Memory
VDDS
WAITF
DQ0-DQ15
E1S
GS
WS
E2S
UBS
LBS
4Mbit
SRAM
VSS
AI08756b
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