LH5164AV
CMOS 64K (8K × 8) Static RAM
DATA RETENTION CHARACTERISTICS (TA = –10°C to +70°C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
Data retention supply voltage VCCDR
CE2 ≤ 0.2 V or
CE1 ≥ VCCDR – 0.2 V
2.0
Data retention supply current
ICCDR
VCCDR = 3 V,
CE2 ≤ 0.2 V or
CE1 ≥ VCCDR – 0.2 V
TA =
25°C
TA =
40°C
Chip disable to data retention
tCDR
0
Recovery time
tR
tRC
NOTES:
1. CE2 should be ≥ VCCDR – 0.2 V or ≤ 0.2 V when CE1 ≥ VCCDR – 0.2 V.
2. tRC = Read cycle time.
MAX.
5.5
0.2
0.4
0.6
UNIT
V
µA
µA
µA
ns
ns
NOTE
1
1
2
CE1 CONTROL (NOTE)
VCC
2.7 V
CE1
VCC - 0.5 V
VCCDR
0V
CE2 CONTROL
VCC
CE2
2.7 V
tCDR
tCDR
DATA RETENTION MODE
tR
CE1 ≥ VCCDR - 0.2 V
DATA RETENTION MODE
tR
VCCDR
0.2 V
0V
CE2 ≤ 0.2 V
NOTE: To control the data retention mode at CE1, fix the input level of CE2 between
VCCDR to VCCDR - 0.2 V or 0 V and 0.2 V during the data retention mode.
Figure 4. Data Retention Characteristics
5164AV-7
6