Table 2. ALGORITHM SELECT BITS
ALGORITHM SELECTED
AS2
AS1
AS0
64kbps to/from 32kbps
0
0
0
64kbps to/from 24kbps
1
1
1
64kbps to/from 16kbps
1
0
1
Figure 5. INPUT TIME SLOT REGISTER
(MSB)
—
—-
D5
D4
D3
D2
SYMBOL
—
—
POSITION
FUNCTION
ITR.7
Reserved. Must be 0 for proper operation
ITR.6
Reserved. Must be 0 for proper operation
D5
ITR.5
MSB of input time slot register
D4
ITR.4
—
D3
ITR.3
—
D2
ITR.2
—
D1
ITR.1
—
D0
ITR.0
LSB of input time slot register
Figure 6. OUTPUT TIME SLOT REGISTER
(MSB)
—
—
D5
D4
D3
D2
SYMBOL POSITION
FUNCTION
—
OTR.7 Reserved. Must be 0 for proper operation
—
OTR.6 Reserved. Must be 0 for proper operation
D5
OTR.5 MSB of output time slot register
D4
OTR.4 —
D3
OTR.3 —
D2
OTR.2 —
D1
OTR.1 —
D0
OTR.0 LSB of output time slot register
6 of 17
DS2165Q
(LSB)
D1
D0
(LSB)
D1
D0