HM62256A Series
Read Timing Waveform (3) *3 *5 *6
CS
Dout
tACS
tCLZ *2
HM62256A Series
Valid Data
*1,*2
tCHZ
Notes: 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit
conditions and are not referenced to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. WE is high for read cycle.
4. Device is continuously selected, CS = VIL.
5. Address Valid prior to or coincident with CS transition Low.
6. OE = VIL.
Write Cycle
HM62256A-8 HM62256A-10 HM62256A-12 HM62256A-15
โโโโโโ โโโโโโ โโโโโโ โโโโโโ
Parameter
Symbol Min Max Min Max Min Max Min Max Unit Note
โโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโ
Write cycle time
tWC
85 โ 100 โ 120 โ 150 โ ns
โโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโ
Chip selection to
end of write
tCW
75 โ 80 โ 85 โ 100 โ ns 2
โโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโ
Address setup time
tAS
0
โ0
โ0
โ0
โ
ns
3
โโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโ
Address valid to
end of write
tAW
75 โ 80 โ 85 โ 100 โ ns
โโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโ
Write pulse width
tWP
55 โ 60 โ 70 โ 90 โ ns 1
โโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโ
Write recovery time tWR
0
โ0
โ0
โ0
โ
ns
4
โโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโ
WE to output in high-Z tWHZ
0
30 0
35 0
40 0
50 ns
10
โโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโ
Data to write time
tDW
40 โ 40 โ 50 โ 60 โ ns
overlap
โโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโ
Data hold from
write time
tDH
0
โ0
โ0
โ0
โ
ns
โโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโ
Output active from
tOW
5
โ5
โ5
โ5
โ
ns
10
end of write
โโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโ
Output disable to
output in high-Z
tOHZ
0
30 0
35 0
40 0
50 ns
10, 11
โโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโ
8