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DESCRIPTION

The 74HC/HCT595 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT595 is an 8-stage serial shift register with a storage register and 3-state outputs. The shift register and storage register have separate clocks.

FEATURES

• 8-bit serial input

• 8-bit serial or parallel output

• Storage register with 3-state outputs

• shift register with direct clear

• 100 MHz (typical) shift out frequency

• ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V.

APPLICATIONS

• Serial-to-parallel data conversion

• Remote control holding register.

8-bit Serial-Input/Serial or parallel-output shift register with Latched 3-State outputs
High-Performance Silicon-Gate CMOS

The SL74HC595 is identical in pinout to the LS/ALS595. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
The SL74HC595 consists of an 8-bit shift register and an 8-bit D-type latch with three-state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8-bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register.

• outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 μA
• High Noise Immunity Characteristic of CMOS Devices

DESCRIPTION
The 74LV595 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT595.
   
FEATURES
• Optimized for Low Voltage applications: 1.0V to 3.6V
• Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V
• Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V,
    Tamb = 25°C
• Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V,
    Tamb = 25°C
• 8-bit serial input
• 8-bit serial or parallel output
• Storage register with 3-State outputs
• shift register with direct clear
• output capability:
    – parallel outputs; bus driver
    – serial output; standard
• ICC category: MSI
   
APPLICATIONS
• Serial-to-parallel data conversion
• Remote control holding register
   

8-bit Serial-Input/Serial or parallel-output shift register with Latched 3-State outputs
High-Performance Silicon-Gate CMOS

The SL74HC595 is identical in pinout to the LS/ALS595. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
The SL74HC595 consists of an 8-bit shift register and an 8-bit D-type latch with three-state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8-bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register.

• outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 μA
• High Noise Immunity Characteristic of CMOS Devices

8-bit Serial-Input/Serial or parallel-output shift register with Latched 3-State outputs

The MC74HC595A consists of an 8−bit shift register and an 8−bit D−type latch with three−state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8−bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register.
The HC595A directly interfaces with the SPI serial data port on CMOS MPUs and MCUs.

• output Drive Capability: 15 LSTTL Loads
• outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 μA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 328 FETs or 82 Equivalent Gates
• Improvements over HC595
   • Improved Propagation Delays
   • 50% Lower Quiescent Power
   • Improved Input Noise and Latchup Immunity

8-bit Serial or Parallel-Input/Serial-output shift register with 3-State output
High–Performance Silicon–Gate CMOS

The MC74HC589A device consists of an 8–bit storage latch which feeds parallel data to an 8–bit shift register. Data can also be loaded serially (see Function Table). The shift register output, QH, is a three–state output, allowing this device to be used in bus–oriented systems.
The HC589A directly interfaces with the SPI serial data port on CMOS MPUs and MCUs.

• output Drive Capability: 15 LSTTL Loads
• outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 526 FETs or 131.5 Equivalent Gates

8-bit Serial or Parallel-Input/Serial-output shift register
High-Performance Silicon-Gate CMOS

The SL74HC165 is identical in pinout to the LS/ALS165. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
This device is an 8-bit shift register with complementary outputs from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Serial shift/ Parallel Load input is low, the data is loaded asynchronously in parallel. When the Serial shift/Parallel Load input is high, the data is loaded serially on the rising edge of either Clock or Clock Inhibit (see the Function Table).
The 2-input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit.

• outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices

8-bit Serial or Parallel-Input/Serial-output shift register
High–Performance Silicon–Gate CMOS

The MC74HC165A is identical in pinout to the LS165. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device is an 8–bit shift register with complementary outputs from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Serial shift/Parallel Load input is low, the data is loaded asynchronously in parallel. When the Serial shift/Parallel Load input is high, the data is loaded serially on the rising edge of either Clock or Clock Inhibit (see the Function Table).
The 2–input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit.

• output Drive Capability: 10 LSTTL Loads
• outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 286 FETs or 71.5 Equivalent Gates

The IN74HC595A is identical in pinout to the LS/ALS595. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The IN74HC595A consists of an 8-bit shift register and an 8-bit D type latch with three-state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8-bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register.

• outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

General Description
The 74F673A contains a 16-bit serial-in, serial-out shift register and a 16-bit parallel-out storage register. A single pin serves either as an input for serial entry or as a 3-STATE serial output. In the Serial-Out mode, the data recirculates in the shift register.
   
Features
■ Serial-to-parallel converter
■ 16-bit serial I/O shift register
■ 16-bit parallel-out storage register
■ Recirculating serial shifting
■ Recirculating parallel transfer
■ Common serial data I/O pin
■ Slim 24 lead package